Circuit recognising change of logic signal state - has pulse generator, coupled to each input terminal, activated at change of logic signal at input terminal

摘要

Generators produce a combined logic signal from the pulses provided by the pulse generators. A bistable logic unit has two input nodes and an output node, the first input node being coupled to the combined logic signal generators. The output node is switched to a first logic state from a second logic state in response to the combined logic signal at the first input node. A delay is connected to the combined logic signal generators and to the second input node of the bistable logic unit for the combined logic signal delay to the second input node. The bistable logic unit has a set/reset buffer memory. USE/ADVANTAGE - For MOS detector circuit for input change, with recognition of input change or transition at several input terminals.