method and arrangement for adapting a measure on a plesiochrones datensignal and its abtakten with the adjusted measure.

摘要

From the clock (T1), further clocks (T2-Tn) are to be derived via a transit-time chain (3-6) so that a clock sequence (T1-Tn) with the same phase intervals is produced. These clocks (T1 to Tn) are derived from the data signal (D1) in edge-triggered D-flip-flops (7-11). A difference between the logic states at the Q outputs of two adjacent D-flip-flops (7-11) produces a preselection of the optimally adapted clock. On the basis of the Q and QN outputs of the D-flip-flops (7-11) and the non-inverting and inverting outputs of amplifiers (12-16), a gate array (18) connects an optimally adapted clock (CLK*) through to the clock output (21). The data signal (D1) is delayed in a delay component (17) by the time required for the selection of the optimally adapted clock (CLK*). The latter then clocks the delayed data signal (D2) in the edge-triggered D-flip-flop (19). …??The arrangement is suitable for use in high-speed block switching systems with a local or central clock supply. …IMAGE…