The processor (cpu) is composed of several units of execution microprogrammed (rad, bdp, pwf) communicating with each other and with a memory (mu) by means of a cache memory (ca). One of the units is an addressing unit (rad). br / to enable the units operate independently, each unit comprises its own control unit and the synchronization means in order to allow or to interrupt the execution of the microprogram defined by the instruction is in progress in said unit. & br / each control unit comprises means of control of the instructions in order to initiate the execution of the micro-program of the first instruction standby. The last microinstruction includes an indication of the end of the microprogram and for certain units, an indication of the anticipation for conditioning the control means so as to allow the execution of the micro-program of the instruction in a waiting position before a preceding instruction is not completely terminated. & br / application to the data processing systems using of the processors optimized for executing the instructions.
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