首页> 外国专利> Implanted semiconductor circuit for ASIC Integrated Circuits, using amplifier-separators on substrate with unitary cell - has balanced pairs of p-channel and n-channel transistors with line feeds running horizontally and implanted layer connections running vertically.

Implanted semiconductor circuit for ASIC Integrated Circuits, using amplifier-separators on substrate with unitary cell - has balanced pairs of p-channel and n-channel transistors with line feeds running horizontally and implanted layer connections running vertically.

机译:用于ASIC集成电路的植入式半导体电路,在具有单体电池的基板上使用放大器-隔离器-拥有平衡的p沟道和n沟道晶体管对,其馈线水平运行,而注入层连接则垂直运行。

摘要

The semiconductor forms a Large Scale Integration chip assembly by implantation. Each module is for the MCM type having an amplifier/separator (BF) and a Unitary feed cell (UC). The Unitary Cell is made up of two symmetrical channels with two p-type transistors (22) and two n-type transistors (23), connected vertically. Horizontal feed lines connect Vdd to the p-channels (20) and Vss to the n-channels (21). Similarly two symmetrical channels are formed for the amplifier/separator, with two p-channel transistors (32) formed and fed from the Voltage line Vdd, and two n-channel transistors formed and fed from the voltage line Vss. ADVANTAGE- Problems experienced with previous semiconductors due to different rise and fall times are eliminated, eliminating timing problems for integrated circuit.
机译:半导体通过注入形成大规模集成芯片组件。每个模块都是MCM类型的,具有一个放大器/分离器(BF)和一个单元馈电单元(UC)。单体电池由两个对称的通道组成,两个对称的通道垂直连接两个p型晶体管(22)和两个n型晶体管(23)。水平馈线将Vdd连接到p通道(20),将Vss连接到n通道(21)。类似地,形成用于放大器/分离器的两个对称沟道,其中形成两个p沟道晶体管(32)并从电压线Vdd馈入,并且形成两个n沟道晶体管并从电压线Vss馈入。优点-由于不同的上升和下降时间,以前的半导体遇到的问题得以消除,从而消除了集成电路的时序问题。

著录项

  • 公开/公告号FR2697109A1

    专利类型

  • 公开/公告日1994-04-22

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号FR19930012493

  • 发明设计人 KITAGAWA MASAYA;FUJII SHIGERU;

    申请日1993-10-20

  • 分类号H01L23/525;H01L27/118;

  • 国家 FR

  • 入库时间 2022-08-22 04:33:43

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