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Bufferless SCSI to SCSI data transfer scheme for disk array applications

机译:适用于磁盘阵列应用程序的无缓冲SCSI到SCSI数据传输方案

摘要

An array controller including a novel data path structure for effecting data transfers between a host computer system bus and four array busses associated with a RAID level 3 disk array without the utilization of a buffer between the host system and the array. The data path structure includes a host register associated with each array bus, each host register being connected to the host bus for receiving data therefrom; a first array register associated with each array bus, each first array register being connected to a corresponding host register for receiving data therefrom and connected to its associated array bus for providing data thereto; and a second array register associated with each array bus, each second array register being connected to it associated array bus for receiving data therefrom and connected to the host bus for providing data thereto. A state machine coordinates the operation of the host and array registers to effect RAID level 3 read and write transfers between the host system and four array channels. The state machine includes logic for generating, in response to a write request from the host system, strobe signals for effecting the transfer of data from the host bus into the host registers, for effectuating the transfer of data from the host registers into corresponding first array registers, and for bringing about the transfer of data from the first array registers onto their corresponding array busses. In response to a read request, logic within the state machine generates strobe signals which are provided to the second array registers for effecting the transfer of data from the array busses into corresponding second array registers and the transfer of data from the second array registers onto the host bus.
机译:一种阵列控制器,包括新颖的数据路径结构,用于实现主机系统总线与与RAID 3磁盘阵列相关的四个阵列总线之间的数据传输,而无需利用主机系统与阵列之间的缓冲区。数据路径结构包括与每个阵列总线相关联的主机寄存器,每个主机寄存器连接到主机总线以从其接收数据。与每个阵列总线相关的第一阵列寄存器,每个第一阵列寄存器连接到相应的主机寄存器以接收来自其的数据,并连接到其相关的阵列总线以向其提供数据;第二阵列寄存器与每个阵列总线相关联,每个第二阵列寄存器连接到其相关联的阵列总线以从其接收数据,并连接到主机总线以向其提供数据。状态机协调主机和阵列寄存器的操作,以实现主机系统与四个阵列通道之间的RAID 3读写传输。该状态机包括用于响应于来自主机系统的写请求而产生选通信号的逻辑,该选通信号用于实现将数据从主机总线传输到主机寄存器中,以实现将数据从主机寄存器传输到相应的第一阵列中。寄存器,并用于将数据从第一个阵列寄存器传输到其相应的阵列总线上。响应于读取请求,状态机内的逻辑产生选通信号,该选通信号被提供给第二阵列寄存器,以实现数据从阵列总线到相应的第二阵列寄存器的传输以及数据从第二阵列寄存器到第二阵列寄存器的传输。主机总线。

著录项

  • 公开/公告号US5287462A

    专利类型

  • 公开/公告日1994-02-15

    原文格式PDF

  • 申请/专利权人 NCR CORPORATION;

    申请/专利号US19910811481

  • 发明设计人 MAHMOUD K. JIBBE;CRAIG C. MCCOMBS;

    申请日1991-12-20

  • 分类号G06F15/02;

  • 国家 US

  • 入库时间 2022-08-22 04:32:12

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