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Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right
Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right
A processor for collecting boolean conditions of multiple operations includes a condition collection register which may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right, and a processor instruction decoder that decodes one operand register addresses as a read address for the condition collection register, and three operand register addresses as a write address for said condition collection register.
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