Content addressable memory cell and content addressable memory circuit for implementing a least recently used algorithm

摘要

A content addressable memory circuit includes a plurality of CAM cell circuits provided in a matrix of rows and columns, a matching line arranged corresponding to each row, and a rewrite control circuit for generating a rewrite instruct signal according to a signal on the matching line. The CAM cell circuit includes a master memory portion for storing a reference data to be compared, a slave memory portion for storing data of an adjacent word, transfer element for transferring to the master memory portion the data stored in the slave memory portion according to a rewrite instruct signal from the rewrite control circuit, and a comparison/driving portion for comparing an input data transmitted to a bit line with the data stored in the master memory portion to drive an associated matching line according to the comparison result. The stored data in the CAM cell circuit is updated according to a shifting operation. The input data is stored in the CAM cell circuit of a certain address. The least recently accessed data is always stored in the CAM cell circuit of another certain address. A content addressable memory circuit is obtained that executes LRU algorithm at a high speed.