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Digital sukuido

机译:吉吉塔勺

摘要

PURPOSE:To reduce the number of the bits of an incremental and decremental counter by allowing positive and negative to almost alternately appear in the output pulse of a digital SQUID, by applying a bias current having an amplitude modulated waveform to the SQUID. CONSTITUTION:A current to be measured is allowed to flow to a SQUID composed of a superconductive loop containing a superconductive inductance L and two Josephson junctions J1, J2 for coupling a magnetic field are provided to said SQUID. The output of an amplitude modulated waveform generator 1A is connected to the asymmetric injection terminal B of the SQUID to apply a bias current to said AQUID and output is taken out from the injection terminal B to be converted to a feedback current If by an incremental and decremental counter 3, an integrator 4 and a D/A converter 5 and fed back to a superconductive inductance Lf to be coupled with the SQUID. By this method, positive and negative output pulses are almost alternately obtained to suppress the number of the bits of the incremental and decremental counter.
机译:目的:通过向SQUID施加具有幅度调制波形的偏置电流,使正负值几乎交替出现在数字SQUID的输出脉冲中,以减少增量和减量计数器的位数。组成:待测电流流向由一个包含超导电感L的超导环路组成的SQUID,并向该SQUID提供了两个用于耦合磁场的约瑟夫逊结J1,J2。调幅波形发生器1A的输出连接到SQUID的非对称注入端子B,以向所述AQUID施加偏置电流,并且从注入端子B取出输出,以通过增量和反向转换为反馈电流If。递减计数器3,积分器4和D / A转换器5,并反馈到超导电感Lf与SQUID耦合。通过这种方法,几乎​​交替地获得正和负输出脉冲,以抑制递增和递减计数器的位数。

著录项

  • 公开/公告号JPH0690267B2

    专利类型

  • 公开/公告日1994-11-14

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP19870177509

  • 发明设计人 藤巻 則夫;

    申请日1987-07-16

  • 分类号G01R33/035;H01L39/22;

  • 国家 JP

  • 入库时间 2022-08-22 04:27:00

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