Normalization of apparent propagation delay

摘要

An integrated circuit includes a clock alignment circuit (10) having a frequency synthesizer (12) for receiving a reference clock signal (CLKIN) at a lower frequency and for generating phases (CLK1, CLK2, CLK3, CLK4) of an oscillator clock signal at a higher frequency. The oscillator clock signal phases (CLK1, CLK2, CLK3, CLK4) drive a desired clock signal phase generating circuit 26 that generates various phases of the desired clock signal. The desired clock signal phases (CLK1, CLK2, CLK3, CLK4) are systematically compared to the reference clock signal (CLKIN). The phase of the desired clock signal that is determined to align with the reference clock signal (CLKIN) is provided as the desired clock signal output from the integrated circuit such that there is no apparent time delay through the integrated circuit. In an alternate embodiment, a single phase of the desired clock signal is selected and a phase locked loop adjusts the oscillator (20) in the frequency synthesizer (12) to align the selected phase of the desired clock signal with the reference clock signal (CLKIN).