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Operation circuit based on floating-point representation

机译:基于浮点表示的运算电路

摘要

An operation circuit based on a floating-point representation system includes a first bypass line (13a) with respect to a shifter (13), and a second bypass line (15a) with respect to a two's complementer (15). When values of the exponent parts (Ae, Be) of two input operands (A, B) are identical to each other, the mantissa part of one of the input operands bypasses the shifter, and is supplied to an ALU (14). In the other case, the mantissa of one of the input operands passes through the shifter, and is always supplied to the ALU. The mantissa of the other input operand is directly supplied to the ALU. When the values of the exponent parts are identical to each other, an output of the ALU passes through the two's complementer and is output as a final operation result. In other cases, the output of the ALU is directly supplied as the final operation result. The sign of the final operation result is determined by a sign discriminator (16).
机译:基于浮点表示系统的运算电路包括相对于移位器(13)的第一旁路线(13a)和相对于二进制补码器(15)的第二旁路线(15a)。当两个输入操作数(A,B)的指数部分(Ae,Be)的值彼此相同时,输入操作数之一的尾数部分将绕过移位器,并提供给ALU(14)。在另一种情况下,输入操作数之一的尾数将通过移位器,并始终提供给ALU。其他输入操作数的尾数直接提供给ALU。当指数部分的值彼此相同时,ALU的输出将通过两者的补数,并作为最终运算结果输出。在其他情况下,ALU的输出直接作为最终操作结果提供。最终运算结果的符号由符号鉴别器(16)确定。

著录项

  • 公开/公告号EP0332215B1

    专利类型

  • 公开/公告日1995-02-15

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号EP19890104313

  • 发明设计人 TAKAHASHI HIROMASA;

    申请日1989-03-10

  • 分类号G06F7/50;

  • 国家 EP

  • 入库时间 2022-08-22 04:14:05

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