Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture

摘要

The matrix of EPROM memory cells comprises on a semiconductor substrate (1) lines of source and drain (2, 3) parallel and alternated one to another, floating gate areas (8) interposed in a checkerboard pattern between said source and drain lines and control gate lines (12) parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric (10) and aligned with respect to said floating gate areas. Field oxide areas (6) are provided for, formed on the substrate between one and the other of said control gate lines (12) and side fins (9, 13) of the floating gate areas (8) and of the control gate lines (12) superimposed over said field oxide areas (6).