Semiconducteur memory device with improved address discriminating circuit for discriminating an address assigned defective memory cell replaced with redundant memory cell

摘要

For speed-up of a testing operation to see what memory cell in a memory cell array (22) is replaced with a redun­dant memory cell (23), a semiconductor memory device com­prises an address discriminating facility having an activa­tion circuit (26) operative to compare an address indicated by an address signal (ADD) and the address assigned the memory cell replaced with the redundant memory cell for producing a first controlling signal (CNT1), a testing operation controlling circuit (32) responsive to a test mode signal (TS) for producing a second controlling signal (CNT2) and a data write-in circuit (28) responsive to the second controlling signal and producing a test bit of logic "1" level in the presence of the first controlling signal and a test bit of logic "0" level in the absence of the first controlling signal, and the test bit of logic "1" and the test bit of logic "0" are respectively written into the redundant memory cell and the memory cell array so that an address assigned to the memory cell replaced with the redundant memory cell is discriminated through a read-out operation.