Interface circuit with parallel-to-serial binary data converter for measurement sensor peripheral

摘要

The converter (1) accepts binary data under the control of a load command signal, in parallel form and feeds them into a transmission line (2) at the rate of an external clock pulse sequence. A blocking circuit formed of an invertor (8), set/reset flip-flop (10) and an AND gate (4) inhibits loading of parallel data during serial transmission. The data source circuit generates a Data Valid signal whenever a valid set of data is present in stable form at the parallel inputs (Do-Dm). This load command signal is inhibited throughout the duration of the clock pulse sequence.