buszugriffsarbitrierung in digital computers.

摘要

A bus arbitration protocol and accompanying bus arbitration logic for multiple-processor computer systems is described in which each processing module (12,12a) has a local cache (16,16a). Several bus arbitration policies are enforced on contending devices which effectively introduce delay states into the arbitration behavior exhibitied by each device. The bus arbitration protocol employs a distributed method of arbitration control involving an essentially fixed prioritization of arbitrating devices.