Summator of voltages, and mosaic of summators, for thermal imaging apparatus.

摘要

The invention relates to a voltage summing circuit for delayed integration in a thermal imaging apparatus. BR/ This summator is constituted by a transistor (T) mounted in common grid. The source of the transistor is connected to a connection capacitance (C1) which receives a voltage step delivered by an injection circuit which converts the electric charge corresponding to a point of the image into voltage. The drain of the transistor is connected to an integration capacitor (Cd) preloaded at a fixed value. The integration is done by discharging the integration capacitance through the transistor, an amount proportional to the ratio C1 / Cd, and the possible gain of an amplifier. BR/ Application to thermal imaging.