MOS-gated power semiconductor device having overcurrent and over-temperature protection

摘要

Control power voltage Vcc is applied through a first MOSFET 20 connected between the gate pin 16 and the gate electrode 10 of the power device. A second control MOSFET 14 is connected across the power device gate 10 and source 12 electrodes. The first control MOSFET is turned off and the second control MOSFET is turned on in response to a fault condition. The turn off of the first MOSFET limits the current sunk by the gate pin. A boot strap circuit permits the use of all N channel control MOSFETs with an N channel power device, and a trimmable temperature shutdown circuit is provided. A bipolar transistor is also integrated into the chip to prevent conduction of the P well/N epi diode formed in the device substrate.