Interactively tailoring topography of integrated circuit layout in accordance with electromigration model-based minimum width metal and contact/via rules

摘要

An interactive electromigration rule-based topography layout adjustment method is provided as an adjunct to a computer aided design tool, in particular a design rule check (DRC) mechanism using a design rule database for defining topography parameters that conform with a given semiconductor wafer fabrication process. Using a set of customized design rule statements, a DRC program is able (Fig 7) to provide a circuit designer with the ability to identify and interactively change, as necessary, dimensions of portions of branches of interconnect (metal, contacts, vias) within an integrated circuit layout design to allow for electromigration of material statements being customized in accordance with circuit simulated-operation-derived worst-case-current conditions as applied to a prescribed set of electromigration-based minimum width rules for interconnect metal, contacts and vias. IMAGE