A fully differential switched-capacitor biquad low pass filter (40) includes a first stage (54), second stage (56), common-mode circuits (55, 72), and feedback transmission gates (73, 74). The first stage (54) includes a first operational amplifier (47), and the second stage (56) includes a second operational amplifier (69). Glitches, or transients, which are caused by the operational amplifiers (47, 69) operating in slew rate limit mode, are prevented from affecting the differential output signals of the filter (40) when the filter (40) is operating with a continuous time output. This is accomplished by preventing the operational amplifiers (47, 69) from operating in slew rate limit mode, or by adjusting the clock signals such that the output of the filter (40) is not coupled to an operational amplifier (47, 69) that is recovering from operation in slew rate limit mode.
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