Clocking systems and methods for pipelined self-timed dynamic logic circuits

摘要

Clocking systems and methods of the present invention use two or more different clock signals for respective groups or stages of self- timed dynamic (or mousetrap) logic gates. Each clock signal defines a precharging time interval and an evaluation time interval for its respective group or stage of self-timed dynamic logic gates. Using the two or more different clock signals, pipelining of the groups or stages of the self-timed dynamic logic gates can be performed.