Binary multiplication implemented by existing hardware with minor modifications to sequentially designate bits of the operand

摘要

Binary multiplication is performed with existing data processing apparatus to which only minor modifications are required. One operand and a partial product are stored in existing latches of a CPU. The second operand is stored in a shift register which is added to the CPU. The data in the shift register is shifted from the LSB to the MSB, with a "0" being loaded into the LSB. As the bits in the first operand are designated in sequence, the value of the partial product is increased by the value in the shift register if the designated bit is a "1". After the sequencing has designated all the bits of the first operand, the partial product is taken to be the product of the multiplication.