Frequency synthesizer using noninteger division and phase selection

摘要

A frequency synthesizer provides a synthesized signal. The synthesizer includes an oscillator that supplies a fast clock signal to a divider programmable by a digital data. The most significant bits of the digital data are provided to the programmable divider, and the least significant bits are provided to an accumulator that cooperates with the programmable divider to increment by one unit its division rank when the accumulator overflows. The synthesizer further includes a generator for generating n increasing delay phases of the synthesized signal; a comparator for comparing the content of the accumulator with n ranges of possible increasing values; and circuits for selecting, as the synthesized signal, the phase whose rank corresponds to the rank of the range within which the content of the accumulator is comprised.