首页> 外国专利> dejitarukonpiyu which uses the central processing unit and the peripheral device where maximum clock frequency differs - modulation impulse oscillation device which is used for frequency modulation type high-speed operational manner and the particular operational manner in ta, and konpiyu which uses particular operational manner - ta

dejitarukonpiyu which uses the central processing unit and the peripheral device where maximum clock frequency differs - modulation impulse oscillation device which is used for frequency modulation type high-speed operational manner and the particular operational manner in ta, and konpiyu which uses particular operational manner - ta

机译:使用最大时钟频率不同的中央处理单元和外围设备的dejitarukonpiyu-在ta中用于调频型高速操作方式和特定操作方式的调制脉冲振荡装置,以及在特定操作方式中使用的konpiyu-ta

摘要

PURPOSE: To prevent a defect in operation on a main storage device, etc., even if a CPU is replaced and the frequency of a clock is varied by including both OUT and IN pulses in operation pulses of a computer, and altering them and leaving a time between oscillations of both the pulses. ;CONSTITUTION: The input terminal A of a pulse modulating circuit system 2 is connected to the pulse oscillating circuit 1 that the personal computer originally has and when a pulse train that the clock oscillates is inputted to the input terminal A, a modulated pulse train is outputted from the output terminal B. This pulse train consists of pulses twice as many as those of the clock and a long pulse interval and a short pulse interval are alternated. Namely, the CPU reads data out of a main memory 3 at a pulse rise after the short pulse interval and writes data in the memory 3 at a rise after the long pulse interval. The interval from the reading to the writing of the memory 3 is longer than pulse intervals in the modulated pulse train. The pulse intervals are a half as long as the original intervals and the number of operations is twice.;COPYRIGHT: (C)1994,JPO
机译:目的:为了防止在主存储设备等上的操作出现故障,即使将OUT和IN脉冲都包括在计算机的操作脉冲中,并对其进行更改并留下,即使更换了CPU并且改变了时钟频率,两个脉冲振荡之间的时间。 ;构成:脉冲调制电路系统2的输入端子A连接到个人计算机本来具有的脉冲振荡电路1,并且当时钟振荡的脉冲序列输入到输入端子A时,调制脉冲序列为该脉冲串由两倍于时钟脉冲的脉冲组成,并且交替长脉冲间隔和短脉冲间隔。即,CPU在短脉冲间隔之后以脉冲上升从主存储器3中读出数据,并且在长脉冲间隔之后以上升脉冲将数据写到存储器3中。从存储器3的读取到写入的间隔比调制脉冲串中的脉冲间隔长。脉冲间隔是原始间隔的一半,操作次数是原来的两倍。版权所有:(C)1994,JPO

著录项

  • 公开/公告号JP2516548B2

    专利类型

  • 公开/公告日1996-07-24

    原文格式PDF

  • 申请/专利权人 FUKUI DENKI SANGYO KK;

    申请/专利号JP19930090299

  • 发明设计人 TAKEUCHI HIROFUMI;

    申请日1993-04-16

  • 分类号G06F1/04;G06F1/06;G06F1/12;

  • 国家 JP

  • 入库时间 2022-08-22 03:58:23

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