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PROGRAMMABLE LOGIC DEVICE WITH VERIFY CIRCUITRY FOR CLASSIFYING FUSE LINK STATES AS VALIDLY CLOSED, VALIDLY OPEN OR INVALID
PROGRAMMABLE LOGIC DEVICE WITH VERIFY CIRCUITRY FOR CLASSIFYING FUSE LINK STATES AS VALIDLY CLOSED, VALIDLY OPEN OR INVALID
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机译:具有验证电路的可编程逻辑设备,用于将熔断链接状态分类为有效关闭,有效打开或无效
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摘要
A PLD with an array of fuse or anti-fuse links includes verification circuitry configured to classify the links into three zones, corresponding to a 'closed' state zone of low resistance values, an 'open' state zone of high resistance values and a 'forbidden' state zone intermediate the 'closed' and 'open' state zones. Because the ratio between the higher and lower resistance value is typically 200, the verification circuitry includes a switchable two level current source that produces a voltage across the link of correct dynamic range.
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