LOW POWER, HIGH PERFORMANCE, ON-CHIP CACHE WITH NO STALL AFTER A WRITE HIT

摘要

An n-way set associative cache is provided which stores address and information (e.g. data, instructions) blocks in a plurality of respectively associated but independently accessible address and information memory arrays, or banks. The address and information arrays are accessible during different phases of a two phase CPU block. An information array is accessed only if a hit occurred in its associated address array. This arrangement produces a one cycle throughput and a reduction in power consumption.