SWITCHED CURRENT DIFFERENTIATOR SWITCHED CURRENT DIFFERENTIATOR

摘要

A switched current differentiator comprises first and second interconnected current memory cells (M1, M2). An input current is applied to terminal (1) and is fed on line (2) to the current memory cells (M1, M2). A first output current is derived from the first current memory cell (M1) via transistor (T3) and a second output current is derived from the second current memory cell (M2) via transistor (T4). The second output current is inverted (A1) and summed with the first output current. The summed current is inverted (A2) and fed to an output (3) via a switch (S3) on odd phases of a clock signal and is fed directly to the output (3) via a switch (S4) on even phases of a clock signal. A damped differentiator may be formed using a feedback loop (T5, T6, A3, A4, S5, S6). In a fully differential version of the differentiator the inverters (A1 to A4) may be constructed by the correct interconnection of the differential signals i.e. by crossing over connections.