Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory

摘要

A multi-processing computer system including a plurality of central processing units (CPUs) (12) and input/output (I/O) units (18, 20), a system memory (16) including a plurality of DRAM-based memory segments, a system control unit (SCU) (14) for operating the CPUs in a parallel fashion and allowing the CPUs and other system units to controllably access addressable segments of system memory, and an interface for establishing communication between the SCU and the system memory and regulating the transfer of memory commands and associated data. The system memory (16) is configured in the form of at least one independently accessible memory unit having a first dedicated data path for the transfer of read data from addressed memory segments to the interface for transfer to the SCU, a second dedicated data path for transfer of write data received from the SCU through the interface to addressed memory segments, and a third dedicated path for transfer of addresses from the SCU to identify addressed segments of memory.