Multifunctions coupler between a central processing unit of a computer and several peripheral devices of this computer

摘要

Multifunction coupler between a computer central processing unit (CPU) and the various peripheral devices of this latter (OPER1, OPER2), containing at least one item of application microsoftware (PMAS) controlling the transfer of information between the peripheral device (OPER1) and the central processing unit comprising a mother-board (CMI1) associated with at least daughter-board (CFI1, CFI2), the mother-board (CMI1) comprising a first and a second connection interface to the output bus (BUSI) of the central processing unit (CPU) and to the daughter-board (INI1, INI2), and a command and control microprocessor (MIPI) arranged between the first and second interfaces, characterised in that the mother-board (CMI1) comprises a random-access memory (MVI) and a first read-only memory (MPMI) which are connected to the output bus of the microprocessor (BUSMI) and the daughter-board, a second read-only memory (MPFI1, MPFI2), the item of application microsoftware (PMAS) comprising a first part (PMM) contained in the first read-only memory (MPMI) of the mother-board (CMI1), which is common in respect of all the items of application microsoftware (PMAS), and a second part (PMF1) contained in the second read-only memory (MPFI1) of the daughter-board (CFI1) which is specific to the application implemented by the peripheral device associated with the daughter-board (OPER1). …??Applicable to computers. …IMAGE…