How to efficiently move bits between data processors with valid bit shift qualifications and their operands, and how to execute bit shift instructions efficiently

摘要

The data processor 40 includes a source 60 and a receiver 61 address generator AGU _B to update the source and destination addresses for the effective digital signal processing (DSP) function. This data processor 40 has a command decoder 41 that recognizes bit shift commands and often encounters in data interleaving operations. In response to the bit shift command, this command decoder causes source 60 and destination 61 AGU _B to update their present addresses using a variable offset value. This command also causes bus controller 44 to convert these bit addresses into corresponding operand addresses and bit regions. This command also causes bus controller 44 to convert these bit addresses into corresponding operand addresses and bit regions. This bus controller 44 accesses the source and destination operands using the operand addresses. This instruction decoder 40 then causes the execution device 45 to transfer the bits from the source operand indicated by the source bit region to the bit position of the destination operand indicated by the destination bit region.