MEMORY CIRCUIT HAVING A LINE DECODER WITH A DANLINGTON-TYPE SWITCHING STAGE AND A DISCHARGE CURRENT SOURCE

摘要

Memory comprising a line decoder provided with a switching stage of the Darlington type. When the deselection time tau 1 for a line is substantially less than the intrinsic switching time tau 3 for a memory cell (M11...Mnp), a discharge current ID is applied momentarily to the lower line conductor (1'...n') of the line (L1...Ln) which is deselected. To do this, the current source ID is connected to the said lower line conductors (1'...n') via delay circuits (RL1, DL1, RLn, DLn) having a time constant tau 2 lower than tau 3 and at least equal to tau 1. IMAGE