RISC architecture for easy datapath and instruction set expansion

摘要

The present invention relates to a reduced instruction set computer (RISC) structure that can easily extend a data path and an instruction set. The present invention relates to a register file for storing data and to read data required for operation from the register file and to maintain it for a predetermined time. A plurality of first storage means, a plurality of execution means for retrieving the data to perform operations of different functions, an output control means for controlling the output of the operation result, and a result of the operation for a predetermined time; A core block comprising a second storage means for storing in a file, the core block comprising: an input data path carrying data required for operation and an input / output port connected to an output data path carrying calculation result at a boundary of the core block. According to the above configuration, the instruction execution of other arithmetic functions The effect is to easily expand the datapath and instruction set without interruption.