High Performance Dynamic Comparison Circuit and Sense Amplifier Common Mode Deep Filter Circuit

摘要

The present invention describes an apparatus and method for comparing the contents of two digital words to determine whether these words match identically. The high speed comparison circuit of the present invention has a plurality of bit comparison block circuits 0 to N coupled to the matching line in the form of wired OR. Each bit comparison block receives a single bit from the first word A to be compared with the corresponding bit of the second word B. The charge charge precharge circuit is coupled to the matching line to precharge the matching line to a voltage level of Vcc / 2. The match feedback circuit is also coupled to the match line and the charge precharge circuit to improve the rate at which the match line is precharged to a voltage level of Vcc / 2. The latch is coupled to the matching line to electrically latch the state of the matching line following the comparison operation. The comparison circuit of the present invention is dynamic and maintains high performance performance regardless of the word length being compared. The charge sharing precharge circuit of the present invention is coupled to a matching line. The precharge circuit has a CMOS pass gate disposed between the matching line and the matching line and having N-channel and P-channel gates. The inverter acts as a match driver and is coupled between the match and match lines at the input and output of the CMOS pass gate. The input of the pass gate to the N-channel gate is coupled to the input of the P-channel gate through the inverter. N-channel gate is faulty to Vcc through two series-coupled P-channel transistors Receive line and SAE signals, respectively. Early in the comparison cycle, Is driven as low as SAE, turning on the series-coupled P-channel transistors and coupling Vcc to the input of the N-channel gate of the pass gate. The P channel gate of the pass gate is also opened by placing the inverter between the N and P channel gates. This causes the pass gate to turn on so that current passes through the match gate between the match and the match lines. Opening and matching the pass gate and connecting the inverter between the matching lines shorts Vcc to ground. Shorting Vcc to ground causes the matching line to be precharged to Vcc / 2. After a predetermined precharge time, the SAE signal is driven high to turn off the P-channel transistor and to electrically isolate Vcc from the CMOS pass gate and the gate of the matching line. The comparison circuit of the present invention then compares the word A bits with word B as described herein.