25/24 demodulation method of SD-VCR data

摘要

The present invention relates to a 25/24 demodulation method of SD-VCR data, wherein the highest order bits of parallel data in 25-bit units are removed and the remaining 24 bits of data are 8-bit using a demodulation clock divided into 8 serial clocks. As a result, the output is corrected in the same form as that of the error correction coding before data recording, thereby facilitating data processing during reproduction of the SD-VCR data.