A programmable logic device with validated circuit elements that classify validly closed, valid, open, or ineffective fuse connection states. (Programmable logic device with verify circuitry for validating open or invalid,

摘要

A PLD with an array of fuse or anti-fuse connections has a low resistance "closed" zone and a high resistance "open" zone and a "closed" and "open" Quot; prohibited " state, and a verification circuit configured to classify the connection in three zones. Because the ratio between the high and low resistance values is typically 200, the verification circuitry includes two levels of current sources that are switchable to generate voltage across the correct, dynamic range of connections.