Serial bit stream sampling method for high speed data transmission equipment

摘要

The method involves sampling a serial bit stream which includes a clock signal of different frequency to the bitstream itself. The clock signal phase is compared with that of the bitstream. A timeslot of length between that of the sampling period and the bit-length is created, ensuring that the bitstream data signal edges appear within the slot. This is done using a decoder to compare the states (Qo-Qn) of a counter (Z) with two threshold values, and produces corresp. control signals (A,B) in accordance with truth tables for a processing circuit to which the data are input together with the sampling clock signal (T2). The processing circuit emits a ''greater'' signal (G) when the timeslot has moved from the centre of the data edge window prematurely between successive edges of the step clock signal, or a ''smaller'' signal (K) in other circumstances.