Matrix memory, which includes standard blocks, standard sub-blocks, a redundant block and redundant sub-blocks, and an integrated circuit containing a variety of such matrix stores.

摘要

An integrated matrix memory is described which comprises standard sub-blocks and a redundant block. Each of the standard sub-blocks comprise a fixed number of standard sub-blocks. The redundant block comprises one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, delay is minimized.