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A multiprocessor system with a selective amplification of global data.

机译:一种具有选择性放大全局数据的多处理器系统。

摘要

In a multiprocessor system having selective global data replication a plurality of processors communicate each with the other through a system bus, each processor is provided with an interface unit for getting access to the system bus and with a local memory accessible by the processor through a local bus, without need of access to the system bus, global data, used by a plurality of processors, are selectively replicated in the local memory of a plurality of processor, but not all of them, and a processor X, to perform an unseverable sequence of global data read-modify-write operations, first get access to the system bus in order to avoid occurrence of deadlocks and data inconsistency and requests the reading of a global data in another unit connected to the system bus and where the requested data may be missing, but once the system bus has been locked performs a read operation in its own local memory, where the requested data is certainly available, whilst the data received through the system bus in ignored.
机译:在具有选择性全局数据复制的多处理器系统中,多个处理器通过系统总线相互通信,每个处理器都具有用于访问系统总线的接口单元和处理器可通过本地访问的本地存储器。在不需要访问系统总线的总线上,由多个处理器使用的全局数据被选择性地复制到多个处理器的本地存储器中,但不是所有处理器和一个处理器X,以执行不可分割的序列全局数据读-修改-写操作,首先要访问系统总线,以避免发生死锁和数据不一致,并请求在连接到系统总线的另一个单元中读取全局数据,并且请求的数据可能在其中丢失,但是一旦系统总线被锁定,它就会在其自己的本地内存中执行读取操作,在该内存中,请求的数据肯定可用,而通过系统总线处于忽略状态。

著录项

  • 公开/公告号DE69019969T2

    专利类型

  • 公开/公告日1995-11-16

    原文格式PDF

  • 申请/专利权人 BULL HN INFORMATION SYST IT;

    申请/专利号DE1990619969T

  • 发明设计人 BAGNOLI CARLO IT;

    申请日1990-08-28

  • 分类号G06F15/16;

  • 国家 DE

  • 入库时间 2022-08-22 03:41:48

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