method for improving the performance of a multi-stage cachespeichers through forced fehlgriffe

摘要

A computing system includes a processor (101), a system memory (104) containing data utilized by the processor (101) and two cache memories. Each cache memory is connected directly to the processor (101). A first cache memory (102) is connected to the processor (101). A second cache memory (103) is connected to the processor (101) and to the system memory (104). The second cache memory (103) contains a subset of data in the system memory (104). The first cache memory (102) contains a subset of data in the second cache memory (103). Data integrity in the system memory (104) is maintained using the second cache memory (103) only. During the execution of a first instruction data required for execution of the first instruction might not be available in the first cache memory (102). The data required for execution of the first instruction is obtained from the second cache memory (103) and written into the first cache memory (102). If, however, there is an attempt to access from the first cache memory (102) data required for a second instruction, and this attempt to access the first cache memory (102) simultaneously to the time when the data required for execution of the first instruction is being written from the second cache memory (303) to the first cache memory (102), then a cache miss is forced and the second cache memory (103) is accessed for the data required for execution of the second instruction.