Bistable flip-flop programmable non-volatile, with a reduction of interference in read mode, in particular for redundancy memory circuit.

摘要

The cell incorporating two floating-gate transistors (TGF1, TGF2) is programmed by application of a voltage (VPRG) through additional transistors (T5, T6) which have complementary signals (PROG, NPROG) on their gate electrodes. To prevent disturbance in read mode esp. by address signals in the programming paths, two isolating transistors (T15, T16) are interposed between these programming transistors and the drains of the floating-gate transistors. The isolating transistors are driven into conduction by a signal (CAMSEL) only for one programming operation on only one gp. of cells.