Device for mapping a set of interrupt signals generated on a first type bus to a set of interrupt signals defined by a second type bus and combing the mapped interrupt signals with a set of interrupt signals of the second type bus

摘要

A system for mapping a PCI interrupt signal to any EISA interrupt signal, in which sharing is allowed between PCI interrupts as well as between a PCI interrupt and an EISA interrupt. The actual mapping is performed during the Power On Self Test (POST) procedure, where the computer writes appropriate values into a set of MAP and MASK registers. Each MAP and MASK register corresponds to a PCI interrupt. Thus, by programming the appropriate MAP and MASK register to certain values, the corresponding PCI interrupt can be mapped to the desired EISA interrupt signal. A decode logic then produces a set of final interrupt signals based on the state of the PCI interrupt signals, the MAP and MASK registers, and the EISA interrupt signals. The final interrupt signals are provided to an interrupt controller, which responds to the assertion of the final interrupt signals by asserting an interrupt signal to the microprocessor.