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Data Transmission processing system having DMA channels running cyclically to execute data transmission from host to memory and from memory to processing unit successively
Data Transmission processing system having DMA channels running cyclically to execute data transmission from host to memory and from memory to processing unit successively
A data transmission processing system provided between a host unit and peripheral devices including at least a memory device and a processing device. The host unit outputs, to the transmission processing system, DMA transmission process request commands. The data transmission process system includes a DMA control unit, provided with a plurality of DMA channels, for cyclically selecting a DMA channel from the plurality of DMA channels in accordance with a predetermined priority, the plurality of DMA channels being allocated to processes with respect to the peripheral devices, and a DMA execution unit for carrying out a DMA transmission process for transmitting data output from the host unit to the memory device via a selected DMA channel corresponding to the memory device in data transmission timing of the host unit and a DMA transmission process for transmitting data stored in the memory device to the processing device via a selected DMA channel corresponding to the processing device in accordance with the DMA transmission process request commands supplied from the host unit.
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