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Self-synchronizing scrambler/descrambler without error multiplication

机译:自同步扰码器/解扰器,不带错误乘法

摘要

A self-synchronizing scrambler/descrambler arrangement operates in two modes. In the first, or start-up mode, predetermined data is coupled to the scrambler and transmitted to the descrambler. This data is used to "seed", i.e., load, storage devices in the scrambler and descrambler with the same information. After a predetermined time interval, the start-up mode is terminated, and the scrambler and descrambler each operate in a steady-state mode. In this mode, the information loaded in the scrambler and descrambler devices are used to form the scrambler and descrambler key signals. Advantageously, in the steady-state mode, the occurrence of transmission errors does not effect the contents of the storage devices in the scrambler and descrambler. Hence, the prior art problem of error multiplication is avoided. In applications where a number of coded and multiplexed data channels are communicated over the communications channel linking the scrambler and descrambler, this approach allows the use of a single scrambler/descrambler without degrading the coding benefits.
机译:自同步加扰器/解扰器装置以两种模式工作。在第一或启动模式中,预定数据被耦合到加扰器并被发送到解扰器。该数据用于“播种”(即,以相同的信息)在加扰器和解扰器中加载,存储设备。在预定时间间隔之后,启动模式终止,并且加扰器和解扰器均以稳态模式工作。在这种模式下,加扰器和解扰器设备中加载的信息用于形成加扰器和解扰器密钥信号。有利地,在稳态模式下,传输错误的发生不影响加扰器和解扰器中的存储设备的内容。因此,避免了现有技术的错误乘法问题。在通过加扰器和解扰器链接的通信信道上传送多个编码和多路复用数据信道的应用中,这种方法允许使用单个加扰器/解扰器而不会降低编码效益。

著录项

  • 公开/公告号US5530959A

    专利类型

  • 公开/公告日1996-06-25

    原文格式PDF

  • 申请/专利权人 AT&T CORP.;

    申请/专利号US19940245755

  • 发明设计人 DANIEL AMRANY;

    申请日1994-05-18

  • 分类号H04L9/12;

  • 国家 US

  • 入库时间 2022-08-22 03:38:18

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