Method and apparatus for skipping a snoop phase in sequential accesses by a processor in a shared multiprocessor memory system

摘要

A method and apparatus that allows a snoop phase of a memory transaction to be shortened or skipped is described. During processing of a present memory transaction, the ownership of a system bus during previous memory transactions, as well as the data addresses requested for those transactions, are tracked. If the ownership and requested address of the present transaction match those from the previous transaction, a Next Address signal is provided that allows another transaction to proceed before the snoop phase of the present transaction is completed. In alternate embodiments, the ownership and addresses for multiple transactions are tracked and compared with the ownership and addresses of the present transaction. If a match occurs, the Next Address signal is asserted.