Bus cycle timing control circuit having bus cycle enable/disable signal dictated by count means using comparison of predetermined and destination addresses for initial count

摘要

A bus cycle timing control circuit that includes a timing control circuit that responds to a data request form a CPU and generates various read/write control signals for the purpose of controlling a bus cycle, a latch for storing a numerical value N, a register for holding a constant number "0", and a counter that starts counting down from the numerical value N held in the latch in response to the completion of one read/write control control signal. The timing control circuit includes a bus cycle start enable/disable circuit for generating a bus cycle start enable/disable signal which inhibits the start of a next bus cycle until the count value of the counter reaches the number "0" and which permits the start of the next bus cycle when the count value of the counter reaches the number "0".