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Noise suppression in large three state busses during test

机译:测试期间大型三态总线的噪声抑制

摘要

A method for suppressing noise encountered during testing of large semiconductor chips is disclosed herein. Output drivers on the semiconductor chip may occasionally produce errant signals during testing, and such errant signals may be coupled through ground or nearby pins which are asynchronous edge sensitive pins to produce false internal transitions. The false internal transitions can cause the chip to fail the test. The proposed method suppresses the noise by disabling the output drivers during portions of the test which may induce errant signals and enables the output drivers when such potentially errant signals have passed.
机译:本文公开了一种用于抑制在测试大型半导体芯片期间遇到的噪声的方法。半导体芯片上的输出驱动器有时可能会在测试过程中产生错误信号,并且此类错误信号可能会通过接地或附近的引脚(它们是异步边沿敏感引脚)耦合以产生错误的内部跳变。错误的内部转换可能导致芯片无法通过测试。所提出的方法通过在测试的某些部分中禁用输出驱动器来抑制噪声,这可能会引起错误信号,并在此类潜在错误信号通过后启用输出驱动器。

著录项

  • 公开/公告号US5550840A

    专利类型

  • 公开/公告日1996-08-27

    原文格式PDF

  • 申请/专利权人 LSI LOGIC CORPORATION;

    申请/专利号US19940180730

  • 发明设计人 MARK OBRIEN;

    申请日1994-01-12

  • 分类号H04B15/00;

  • 国家 US

  • 入库时间 2022-08-22 03:37:57

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