Apparatus for displaying an image in a reduced scale by sampling out an interlace video signal uniformly in a vertical direction without sampling out successive lines

摘要

An image reduction apparatus is disclosed which can sample and reduce an interlace video signal such as a digital video signal uniformly in a vertical direction without sampling out successive lines. A non- delayed horizontal synchronizing signal and a delayed horizontal synchronizing signal are logically ANDed to obtain a double-speed horizontal synchronizing signal having a double speed to that of the horizontal synchronizing signal. The double-speed horizontal synchronizing signal is sampled in accordance with a vertical reduction rate by a vertical sampling circuit to obtain a vertical sampling signal. In the first field, the vertical sampling signal and a vertical address signal are latched into respective latch circuits in response to the non- delayed horizontal synchronizing signal, but in the second field, the signals are latched similarly in response to the delayed horizontal synchronizing signal. Writing of image data into a frame memory is controlled by the vertical sampling signal outputted from the corresponding latch circuit while designating an address of the frame memory in the vertical direction by the vertical address signal outputted from the corresponding latch circuit.