HIERARCHICAL BUS CONTROL SYSTEM AND BUS BRIDGE

摘要

PROBLEM TO BE SOLVED: To reduce the latency at the time of transferring a transaction from one bus to the other bus by snooping a cache when the transaction is issued to one of a high-order bus or a low-order bus and precedingly executing the arbitration of the other bus before deciding whether or not the transaction is transferred to the other bus. SOLUTION: When the transaction of a high-order bus is inputted to a bus bridge 30, the index part of an address in the transaction is inputted to a tag- read circuit 32 and a tag corresponding to the index is read from a tag RAM 50. The tag is compared with the tag of the actual address in a mis-hit judging circuit 38. At the time of non-coindidence, the mis-hit judging circuit 38 issues a mis-hit signal, it is inputted to an arbitration circuit 44 with an OR circuit 112 and the arbitration of a low-order bus is executed. After that, the transaction to be transferred is issued to the low-order bus.