PROCESSOR FOR HIGH DEFINITION TELEVISION SIGNAL

摘要

PROBLEM TO BE SOLVED: To provide a processor for a high definition television signal with compatibility between EDTV-II and a present television system. SOLUTION: An input composite video signal is A/D-converted to be separated into a luminance signal and a chrominance signal by a Y/C separation circuit 12. An HH-extraction circuit 15 extracts a luminance parallel high frequency signal from this separated chrominance signal, a level control circuit 20 controls this signal, HH-demodulation circuit 26 demodulates the signal and an adder circuit 14 adds the signal to the luminance signal. This demodulated signal is outputted as a Y signal. A signal level detection and judging means composed of an H delay circuit 22, an adder circuit 23, an absolute value arithmetic circuit 24 and an absolute value comparing circuit 25 detects the level of a signal component in a spatial intermediate area between the multiple area of the luminance parallel high frequency signal and that of the chrominance signal from the separated chrominance signal to judge its level to control the level control circuit 20.