PARAMETER INPUT METHOD FOR VERIFICATION OF LOGICAL DESIGN

摘要

PROBLEM TO BE SOLVED: To provide a system (namely, a tool set) for verifying logic on a logic design level. SOLUTION: A stimulus from the outside for logic design is derived from a series of timing drawings generated in accordance with the interface protocol of logic design being a verification object. A timing drawing editor 18 supplies a graphical user interface 16 by which a logic designer can describe his own logic by using a general-purpose timing drawing into which the permutation of interface specification is incorporated. The output of the timing drawing editor 18 is a file for describing the interface of the logic and the plural timing drawings where the different and various interface interactions are mentioned can be stored in the file. A suitable simulation driver reads the file generated by the timing drawing editor 18, and obtains the interface mentioned in the file. Then, simulation/randomization algorithm are applied for operating the interface in an appropriate situation for the interface mentioned in the timing drawing.