PARALLEL CONNECTED-TYPE MASTER REQUEST CLASS STRUCTURE FOR INTERFACING OF PROCESSOR IN PACKET EXCHANGE-TYPE CACHE COHERENT MULTIPROCESSOR SYSTEM

摘要

PROBLEM TO BE SOLVED: To attain the reduction of standby time for processing individual read/write-back transaction pairs together with the total improvement of transaction throughput by providing two parallel independent input request queues at least for storing memory transaction requests. SOLUTION: A multiprocessor computer system 100 is provided with a pair of 'UPA modules' and each UPA module 102 has a port 104. The UPA ports 104 are respectively interfaced through packet exchange type address buses 114 and packet exchange type data buses 116, which are respectively individually operated, to a mutual connection module 112 and a system controller 110. The UPA modules logically connect plugs to the UPA ports. The system controller 110 is a centralized controller, controls the mutual connection module 112 and schedules the transfer of data between two UPA ports 104 or between the UPA port 104 and a memory 108.