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A CIRCUIT PROVIDED WITH FACILITIES FOR IDDQ-TESTING OF A BIAS GENERATOR
A CIRCUIT PROVIDED WITH FACILITIES FOR IDDQ-TESTING OF A BIAS GENERATOR
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机译:提供了用于偏置发生器的IDDQ测试的电路
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摘要
A bias generator is tested in an IDDQ-scheme by applying each respective one of the bias voltages to a respective PFET that is individually gated by a respective NFET. This permits measuring the quiescent currents. Any deviation in the bias voltages is translated into a deviation of the quiescent current.
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